Integrated circuit memory devices are widely used in consumer and commercial applications. As the integration density of integrated circuit memory devices continues to increase, it generally is desirable to increase the operational speed thereof. One widely used integrated circuit memory device is an integrated circuit Dynamic Random Access Memory (DRAM). In order to provide high-speed operations, synchronous DRAMs and Double Data Rate (DDR) DRAMs also have been developed.
Large capacity integrated circuit memory devices such as synchronous DRAM and DDR DRAM devices may have a layout in which a column decoder is vertically arranged as shown in FIG. 1. As shown in FIG. 1, the length in the word line direction may be longer than in the column direction.
Referring now to FIG. 1, a conventional large capacity memory device may include a plurality of memory cell arrays 11 arranged in a matrix of rows and columns, a plurality of sense amplification blocks 13 arranged at either side of each memory cell array 11, a plurality of sub word line drivers (SWD) 15 arranged at the upper and lower ends of the memory cell arrays 11, a plurality of conjunction regions 17 arranged at the upper and lower ends of the sense amplification blocks 13, a column decoder 18 arranged on the left of the matrix of the plurality of memory cell arrays 11, and a row decoder 19 arranged at the lower end of the matrix of the plurality of memory cell arrays 11. It will be understood that as used herein, the terms "upper/lower," "left/right," and "row/column" indicates relative directions and do not indicate absolute orientations.
FIG. 2 is a circuit diagram of sense amplification blocks and conjunction regions of the memory device shown in FIG. 1 using conventional technology. The conjunction regions 27a and 27b are arranged at the upper and lower ends of the sense amplification blocks 23. Each sense amplification block 23 generally has a folded bit line-shared sense amplifier structure. The sense amplification block 23 includes: a) a first switching unit 102 for connecting a first pair of bit lines BLi and BLi to a pair of sensing bit lines SBLi and SBLi in response to a first isolation control signal transmitted through a first isolation control line ISi; b) a first equalizer 100 connected between the first pair of bit lines BLi and BLi for equalizing the first pair of bit lines BLi and BLi in response to a first equalizing signal transmitted through a first equalization control line EQi; c) a second switching unit 106 for connecting a second pair of bit lines BLj and BLj to the pair of sensing bit lines SBLi and SBLi in response to a second isolation control signal transmitted through a second isolation control line ISj; and d) a second equalizer 108 connected between the second pair of bit lines BLj and BLj for equalizing the second pair of bit lines BLj and BLj in response to a second equalizing signal transmitted through a second equalizing control line EQj, and a sense amplifier 104 for sensing the voltage difference between the pair of sensing bit lines SBLi and SBLi and amplifying the voltage difference.
As shown in FIG. 1, a memory cell array (i) is connected to the first pair of bit lines BLi and BLi and a memory cell array (j) is connected to the second pair of bit lines BLj and BLj.
The conjunction regions 27a and 27b include LA and LA drivers for respectively enabling the P-type and N-type sense amplifiers of the sense amplifier 104, a transfer transistor for connecting a local input and output line LIO connected to the sense amplifier 104 to a global input and output line GIO, and a control circuit for controlling the sub word line drivers.
A first isolation control signal, applied to the gates of isolation transistors 34 and 35 of the first switching unit 102, and a second isolation control signal, applied to the gates of the isolation transistors 42 and 43 of the second switching unit 106, are generated from peripheral circuits connected to the first isolation control line ISi and the second isolation control line ISj, i.e., isolation control signal generators 28 and 29.
In a memory device having the structure in which the row decoder is vertically arranged, i.e., the structure in which the length in the wordline direction is long and the local and global input and output lines are used, the length of the first and second isolation control lines ISi and ISj may become longer than those of the structure in which the row decoder is horizontally arranged. Accordingly, the load of the first isolation control line ISi and the second isolation control line ISj, i.e., a parasitic capacitance, may increase, for example, to more than two times the load.
When the memory cell array (i) connected to the first pair of bit lines BLi and BLi is activated and operates, the voltage of first isolation control signal transmitted through the first isolation control line ISi is at a boosted voltage level VPP. The voltage of the second isolation control signal transmitted through the second isolation control line ISj is at ground voltage level VSS. This may reduce the load of the sense amplifier 104 by disconnecting the second pair of bit lines BLj and BLj from the pair of sensing bit lines SBLi and SBLi by turning off the second switching unit 106.
When the load of the second isolation control line ISj is large, the discharging speed of the second isolation control line ISj may be reduced. Accordingly, the point in time at which the second isolation control signal becomes grounded at voltage VSS may be delayed. In this case, the load of the sense amplifier 104 may become larger since the second switching unit 106 is not turned off during the sensing operation. Thus, the second pair of bit lines BLj and BLj are not isolated from the pair of sensing bit lines SBLi and SBLi. Accordingly, the charge sharing time between the first pair of bit lines BLi and BLi and the pair of sensing bit lines SBLi and SBLi may increase. As a result, the operation of the sense amplifier 104 may be delayed.
The size of the driver ports of the isolation control signal generators 28 and 29 connected to the first isolation control line ISi and the second isolation control line ISj may be made as large as possible in a conventional device in an attempt to overcome the large load of the first isolation control line ISi and the second isolation control line ISj. However, since the driving ability of the driver ports may have a limit, even if the sizes of the driver ports are made as large as possible, it still may not be possible to overcome the increased load.